The T3 Sparc servers are up for grabs from Oracle (that still sounds weird).   The four socket box runs 512 threads. 

Larry Ellison’s first Sparc chip and server • The Register

 

The Sparc T3 is a 16-core kicker to the current eight-core Sparc T2+. The initial versions of the Sparc T3 chip come with either 8 or 16 cores activated and run at one clock speed, 1.65 GHz, according to the spec sheet.

The Sparc T3 chips use a 40 nanometer process and are fabbed by Sun’s designated wafer baker for the T3 chips, Taiwan Semiconductor Manufacturing Corp. The chip has a die size of 371mm and like its predecessor offers glueless scalability from one to either two or four sockets. The Sparc T3 chip has eight threads per core and one nine-stage floating point unit per core. The Sparc T3 core has 8 KB of L1 data cache and 16 KB of L1 instruction cache and 6 MB of L2 cache shared by the cores, carved into 16 banks of 384 KB each. The on-chip memory controller supports DDR3 main memory, and Oracle is currently supporting 1.07 GHz sticks in the Sparc T3 systems.

 

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Published in: on September 21, 2010 at 5:43 pm  Leave a Comment  

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